C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 180

• Manufacturer Part Number: C8051F930-TB
• Description: BOARD TARGET/PROTO W/C8051F930
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930-TB

• Contents: Board
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F930
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1472

C8051F93x-C8051F92x
18. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are
unaffected during a reset; any previously stored data is preserved as long as power is not lost. Since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “19. Clocking Sources” on page 187 for information on selecting and
configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12
as its clock source (Section “26.4. Watchdog Timer Mode” on page 311 details the use of the Watchdog
Timer). Program execution begins at location 0x0000.
180
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
Px.x
Px.x
SmaRTClock
System
Clock
Comparator 0
RTC0RE
+
-
C0RSEF
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
DD
CIP-51
Handler
Core
Monitor and power-on resets, the RST pin is driven low until the device
Figure 18.1. Reset Sources
VDD/DC+
WDT
PCA
EN
System Reset
Supply
Monitor
+
-
Rev. 1.1
Enable
(Software Reset)
SWRSF
(wired-OR)
Power Management
Block (PMU0)
'0'
Power On
Reset
VBAT
Illegal Flash
Reset
Operation
System Reset
Power-On Reset
Funnel
Reset
RST