C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 284
![BOARD TARGET/PROTO W/C8051F930](/photos/9/25/92560/c8051f930-tb_sml.jpg)
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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C8051F93x-C8051F92x
SFR Definition 25.2. TCON: Timer Control
SFR Page = 0x0; SFR Address = 0x88; Bit-Addressable
284
Reset
Name
Bit
Type
7
6
5
4
3
2
1
0
Bit
Name
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
R/W
TF1
7
0
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 12.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 12.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
R/W
TR1
0
6
R/W
TF0
5
0
TR0
R/W
Rev. 1.1
4
0
Function
R/W
IE1
3
0
R/W
IT1
2
0
R/W
IE0
1
0
R/W
IT0
0
0
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