C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 119
![BOARD TARGET/PROTO W/C8051F930](/photos/9/25/92560/c8051f930-tb_sml.jpg)
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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10.7. EMIF Special Function Registers
The special function registers used by the EMIF are EMI0CN, EMI0CF, and EMI0TC. These registers are
described in the following register descriptions.
SFR Definition 10.1. EMI0CN: External Memory Interface Control
SFR Page = 0x0; SFR Address = 0xAA
Reset
Name
Bit
7:5
4:0
Type
Bit
Unused
Name
PGSEL
R/W
7
0
Unused.
Read = 000b; Write = Don’t Care
XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
determines which page of XRAM is accessed. When the MSB of PGSEL is set to 1
and the EMIF is configured for one of the two split-modes, 8-bit MOVX instructions
target off-chip memory.
For Example:
If EMI0CN = 0x01, addresses 0x0100 through 0x01FF of on-chip memory will be
accessed.
If EMI0CN = 0x0F, addresses 0x0F00 through 0x0FFF of on-chip memory will be
accessed.
If EMI0CN = 0x11, addresses 0x0100 through 0x01FF of off-chip memory will be
accessed.
If EMI0CN = 0x1F, addresses 0x0F00 through 0x0FFF of off-chip memory will be
accessed.
R/W
0
6
R/W
5
0
R/W
Rev. 1.1
4
0
Function
C8051F93x-C8051F92x
R/W
3
0
PGSEL[4:0]
R/W
2
0
R/W
1
0
R/W
0
0
119
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