AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 1104

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

36.5.6
36.6
36.6.1
36.6.2
36.6.2.1
36.6.2.2
9166C–AVR-08/11
Functional Description
Debug Operation
ADC Resolution
ADC Conversion Modes
S/H versus DIRECT conversions
Differential / single ended
When an external debugger forces the CPU into debug mode:
The ADC supports 8-bit, 10-bit or 12 bits resolutions. Precision can be set differently for each
sequencer by setting the SRES bits in the SEQCFGx register. By default, after a reset, the reso-
lution is set to 12 bits. To get full resolution, the user should first calibrate the ADC as detailed in
Section
The ADC is fully differential. To perform single ended measures, the user can perform pseudo
unipolar conversions by connecting ground onto the negative input. User can connect it to an
external ground through pads or internal ground depending on if there's one connected onto the
negative input multiplexer. Since conversion results are always 12 bits in 2's complement repre-
sentation, the sign bit will not change, and then the resulting resolution is 11 bits max.
By default S/H are enabled, to change that setting, set the Sample and Hold disable bit (SHD)
located in the CFG register. Maximum accuracy is achieved when disabling S/H but setting this
bit forbids dual sequencer mode, Sequencer 1 is then switched off. Furthermore, in this mode
S/H are switched off to lower power consumption.
Table 36-2.
S/H
DIRECT
• the ADCIFA continues normal operation if the bit related to ADCIFA in PDBG register is ‘0’.
• the ADCIFA is frozen if the bit related to ADCIFA in PDBG register is ‘1’. When the ADCIFA is
PDCA access continues normal operation and may interfere with debug operation.
frozen, ADCIFA PB registers can still be accessed. Then, reading registers may modify
status bits (OVRx, LOVRx) like in normal operation. PDCA access are pending.
Mode
36.6.16.
Characteristics
Pros
Cons
Pros
Cons
S/H versus DIRECT Conversions
Gain setting (1, 2, 4, 8, 16, 32, 64)
Dual sequencer mode
Reduced accuracy
Dynamic limitation (fixed with over-sampling)
1 ADC clock period spent to propagate into S/H
No dynamic limitation due to S/H
Full accuracy
Saves 1 ADC clock period compared to the features list timings
No gain
Single sequencer mode only
AT32UC3C
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