AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 354

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

Figure 19-6. Read Burst with Boundary Row Access
19.7.5
9166C–AVR-08/11
SDRAMC_A[12:0]
D[15:0]
SDWE
SDCS
SDCK
RAS
CAS
SDRAM Controller Refresh Cycles
Col a
Row n
Col b
Dna
An auto refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto refresh automatically.
The SDRAMC generates these auto refresh commands periodically. An internal timer is loaded
with the value in the Refresh Timer Register (TR) that indicates the number of clock cycles
between successive refresh cycles.
A refresh error interrupt is generated when the previous auto refresh command did not perform.
In this case a Refresh Error Status bit is set in the Interrupt Status Register (ISR.RES). It is
cleared by reading the ISR register.
When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not
delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is
busy and the master is held by a wait signal. See
Col c
Dnb
Col d
Dnc
Dnd
T
RP
= 3
Row m
T
RCD
= 3
Figure 19-7 on page
Col a
CAS = 2
Col b
Dma
Col c
355.
Dmb
Col d
AT32UC3C
Dmc
Col e
Dmd
Dme
354