AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 491

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

24.5.4
9166C–AVR-08/11
Transmit Buffer
The System Bus specification requires that bursts should not cross 1K boundaries. As receive
buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to
write the pointer register with the least three significant bits set to zero. As receive buffers are
used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used.
If a receive error is detected the receive buffer currently being written is recovered. Previous buf-
fers are not recovered. Software should search through the used bits in the buffer descriptors to
find out how many frames have been received. It should be checking the start-of-frame and end-
of-frame bits, and not rely on the value returned by the receive buffer queue pointer register
which changes continuously as more buffers are used.
For CRC errored frames, excessive length frames or length field mismatched frames, all of
which are counted in the statistics registers, it is possible that a frame fragment might be stored
in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a
buffer following a buffer with no end of frame bit set.
For a properly working Ethernet system, there should be no excessively long frames or frames
greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long.
Therefore, it is a rare occurrence to find a frame fragment in a receive buffer.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then
the buffer has already been used and cannot be used again until software has processed the
frame and cleared bit zero. In this case, the DMA interface sets the buffer not available bit in the
receive status register and triggers an interrupt.
If bit zero is set when the receive buffer manager reads the location of the receive buffer and a
frame is being received, the frame is discarded and the receive resource error statistics register
is incremented.
A receive overrun condition occurs when bus was not granted in time or because HRESP was
not OK (bus error). In a receive overrun condition, the receive overrun interrupt is asserted and
the buffer currently being written is recovered. The next frame received with an address that is
recognized reuses the buffer.
If bit 17 of the network configuration register is set, the FCS of received frames shall not be cop-
ied to memory. The frame length indicated in the receive status field shall be reduced by four
bytes in this case.
Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be
between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum
length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number
of buffers permitted for each transmit frame is 128.
The start location for each transmit buffer is stored in memory in a list of transmit buffer descrip-
tors at a location pointed to by the transmit buffer queue pointer register. Each list entry consists
of two words, the first being the byte address of the transmit buffer and the second containing
the transmit control and status. Frames can be transmitted with or without automatic CRC gen-
eration. If CRC is automatically generated, padding is also automatically generated to take
frames to a minimum length of 64 bytes.
buffer descriptor list. To transmit frames, the buffer descriptors must be initialized by writing the
right byte address to bits 0 through 31 in the first word of each list entry. The second transmit
buffer descriptor is initialized with control information that indicates the length of the buffer,
Table 24-2 on page 492
defines an entry in the transmit
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