AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 897

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

32.6.3.12
9166C–AVR-08/11
RXINI
FIFOCON
IN
Management of OUT pipes
• Multi packet mode for IN pipes
• Overview
• Detailed description
(bank 0)
DATA
RXINI
FIFOCON
RXINI should always be cleared before clearing FIFOCON to avoid missing an RXINI event.
Figure 32-19. Example of an IN pipe with one data bank
Figure 32-20. Example of an IN pipe with two data banks
See
IN pipe.
OUT packets are sent by the host. All the data can be written, acknowledging whether or not the
bank is full.
The pipe and its descriptor in RAM must be pre configured.
When the current bank is clear, the Transmitted OUT Data Interrupt (TXOUTI) and FIFO Control
(UPSTAn.FIFOCON) bits will be set simultaneously. This triggers a PnINT interrupt if the Trans-
mitted OUT Data Interrupt Enable bit (UPCONn.TXOUTE) is one.
IN
”Multi packet mode for OUT endpoints” on page 888
ACK
HW
(bank 0)
DATA
SW
read data from CPU
BANK 0
ACK
HW
SW
SW
read data from CPU
IN
BANK 0
IN
(bank 1)
DATA
(bank 0)
DATA
and just replace OUT endpoints with
SW
ACK
HW
ACK
HW
AT32UC3C
read data from CPU
read data from CPU
SW
SW
BANK 1
BANK 0
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