AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 969

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

33.6.2.2
9166C–AVR-08/11
Comparator
The comparator continuously compares its counter value with the channel period defined by
CPRD in the
CDTY in the
OCx accordingly.
The different properties of the waveform of the output OCx are:
• the clock selection. The channel counter is clocked by one of the clocks provided by the
• the waveform period. This channel parameter is defined in the CPRD field of the CPRDx
• the waveform duty-cycle. This channel parameter is defined in the CDTY field of the CDTYx
clock generator described in the previous section. This channel parameter is defined in the
CPRE field of the
register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1,
2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM internal clock (CCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
X CPRD
CRPD
2
2
duty cycle
×
×
×
duty cycle
CCK
X CPRD
CPRD DIVA
CCK
CCK
×
CCK
×
DIVA
”Channel Duty Cycle Register” on page 1036
”Channel Period Register” on page 1038
)
×
=
)
)
=
or
(
------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
(
---------------------------------------------------------------------------------------------------------------------- -
)
(
”Channel Mode Register” on page 1034
period 2 ⁄
or
(
----------------------------------------- -
CRPD DIVB
(
--------------------------------------------------- -
2 CPRD
–
×
CCK
×
⁄
) 1 fchannel_x_clock
CCK
–
×
period
⁄
)
(
DIVB
period 2 ⁄
)
)
×
CDTY
×
(CPRDx) and the duty-cycle defined by
CDTY
)
(CDTYx) to generate an output signal
(CMRx). This field is reset at 0.
) )
AT32UC3C
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