AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 599

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

25.6.8.4
25.6.8.5
25.6.8.6
9166C–AVR-08/11
Receiver and Transmitter Control
Character Transmission
Character Reception
See Section “25.6.2” on page 570.
The characters are sent by writing in the Transmit Holding Register (THR). An additional condi-
tion for transmitting a character can be added when the USART is configured in SPI master
mode. In the MR register, the value configured on INACK field can prevent any character trans-
mission (even if THR has been written) while the receiver side is not ready (character not read).
When INACK equals 0, the character is transmitted whatever the receiver status. If INACK is set
to 1, the transmitter waits for the receiver holding register to be read before transmitting the
character (RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver
side.
The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmit-
ter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the
characters written in THR have been processed. When the current character processing is com-
pleted, the last character written in THR is transferred into the Shift Register of the transmitter
and THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in
THR while TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding
Register (THR) is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays
at high level during all this time. The UNRE bit is cleared by writing the Control Register (CR)
with the RSTSTA (Reset Status) bit at 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit before the trans-
mission of the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So,
the slave select line (NSS) is always released between each character transmission and a mini-
mum delay of 3 Tbits always inserted. However, in order to address slave devices supporting the
CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at
low level by writing the Control Register (CR) with the RTSEN bit at 1. The slave select line
(NSS) can be released at high level only by writing the Control Register (CR) with the RTSDIS
bit at 1 (for example, when all data have been transferred to the slave device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS)
to initiate a character transmission but only a low level. However, this low level must be present
on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to
the MSB bit.
When a character reception is completed, it is transferred to the Receive Holding Register
(RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while
RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into RHR
and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (CR)
with the RSTSTA (Reset Status) bit at 1.
To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the
frame must ensure a minimum delay of 1 Tbit between each character transmission. The
receiver does not require a falling edge of the slave select line (NSS) to initiate a character
reception but only a low level. However, this low level must be present on the slave select line
(NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.
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