AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 955

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

32.7.3.14
Register Name:
Access Type:
Offset:
Reset Value:
• INITBK: Bank Initialization
• INITTGL: Data Toggle Initialization
• PFREEZE: Pipe Freeze
• FIFOCON: FIFO Control
• NBUSYBKE: Number of Busy Banks Interrupt Enable
9166C–AVR-08/11
31
23
15
7
-
-
-
-
This bit is always read as zero.
If the user writes a one to the INITBKC bit, this will set the current bank to Bank0 value for the current pipe.
If the user writes a one to the INITBKS bit, this will set the current bank to Bank1 value for the current pipe.
This may be useful to restore a pipe to manage alternate pipes on the same physical pipe.
This bit is always read as zero.
If the user writes a one to the INITTGLC bit, this will set the Data toggle to Data0 value for the current pipe.
If the user writes a one to the INITTGLS bit, this will set the Data toggle to Data1 value for the current pipe.
This may be useful to restore a pipe to manage alternate pipes on the same physical pipe.
This bit is cleared when the PFREEZEC bit is written to one. This will enable the pipe request generation.
This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has
been received on this pipe, or when INRQ In requests have been processed, or after a pipe Enable (UPRST.PEN rising). This
will freeze the pipe requests generation.
If the user clears the PFRFEEZEC bit while a transaction is on going on the USB bus, the transaction will be properly completed
and then the PFREEZE bit will be cleared.
For OUT and SETUP pipes:
This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.
This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.
For IN pipes:
This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.
This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).
Pipe n Control Register
RXSTALLDE/
CRCERRE
FIFOCON
30
22
14
6
-
-
UPCONn, n in [0..6]
Read-Only
0x05C0 + (n * 0x04)
0x00000000
ERRORFIE
29
21
13
5
-
-
-
NBUSYBKE
NAKEDE
28
20
12
4
-
-
PERRE
INITBK
27
19
11
3
-
-
RAMACERE
INITDTGL
TXSTPE
26
18
10
2
-
PFREEZE
TXOUTE
25
17
9
1
-
-
AT32UC3C
RXINE
24
16
8
0
-
-
-
955