AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 458

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

23.6.2.8
9166C–AVR-08/11
CPU Local Bus
Figure 23-4. Interrupt Timing with Glitch Filter Disabled
Figure 23-5
enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges. In
the example, the first pulse is rejected while the second pulse is accepted and causes an inter-
rupt request.
Figure 23-5. Interrupt Timing with Glitch Filter Enabled
The CPU Local Bus can be used for application where low latency read and write access to the
Output Value Register (OVR) and Output Drive Enable Register (ODER) is required. The CPU
Local Bus allows the CPU to configure the mentioned GPIO registers directly, bypassing the
shared Peripheral Bus (PB).
To avoid data loss when using the CPU Local Bus, the CLK_GPIO must run at the same fre-
quency as the CLK_CPU. See
The CPU Local Bus is mapped to a different base address than the GPIO but the OVER and
ODER offsets are the same. See the CPU Local Bus Mapping section in the Memories chapter
for details.
CLK_GPIO
CLK_GPIO
Pin Level
Pin Level
IFR
IFR
shows the timing for rising edge (or pin-change) interrupts when the glitch filter is
Section 23.5.2
for details.
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