AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 1108

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

36.6.5
36.6.6
9166C–AVR-08/11
ADC Clock Configuration (CKDIV)
ADC Multiplexers Settle Time
Figure 36-5. Using FRM and Converting at Full Speed
The clock frequency range for the ADC is [1.5 MHz - 32 KHz]. Since the ADC interface uses the
system clock up to the PB maximum frequency, a clock downscale must be done if a higher fre-
quency system clock is used. This scaling may also be done in order to slow down the ADC
conversions or increase the S/H time, without affecting the system clock. The downscale is done
by writing the maximum counter value in the Counter Value (CNT) field of the CKDIV register,
with a possible division factor from 1 to 512 giving the following transfer function:
T(CkADC)= T(CkPB)
setting the ADCEN bit in the CFG register.
Figure 36-6. Clock Generator Block Diagram
In addition when CKDIV is written, the internal counter is reset to avoid rollover phenomena: DO
NOT WRITE CKDIV WHEN PERFORMING CONVERSIONS.
F(CkPB) should at least be 4 times greater than F(CkADC) to make the ADC controller work
properly.
By default, channel multiplexers settle time is set to half a PB clock period. If operating with a
high PB clock frequency, then MUX settle time can be increased to achieve a 1.5 PB clock peri-
ods settle time by writing a one in the MUXSET field in the CFG register. For more information,
please refer to the ADC electrical characteristics.
[115 KHz - PB max
CkPB ADCIFA
frequency]
·
((CNT + 1)
DIVIDE BY CNT
·
2). The divider is enabled as soon as the ADC is enabled by
CKDIV :
/2
[32 KHz - 2 MHz]
AT32UC3C
CkADC
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