AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 1115

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

36.6.16.2
36.6.16.3
36.6.17
36.6.18
9166C–AVR-08/11
Window Monitor
Arbitration
ADC offset error calibration
Sample and hold gain error calibration
Offset cancellation has to be performed by the user due to temperature and operating voltage
conditions dependence. The offset can be obtained by converting a null differential value. That
offset has to be negated and written into the Offset Calibration (OCAL) field of the ADCCAL reg-
ister. Then, for each conversion result, the controller will return the converted value added with
the signed OCAL value. For instance, if the offset value obtained is 0x3, then the value 0xFD
must be written to OCAL. Please note that OCAL is a 6 bits register, if the MSB is high then the
value will be considered negative. A saturation mechanism avoids flipping phenomena. OCAL
stores a signed number of LSB assuming the calibration has been performed in 12 bits resolu-
tion. If converting at a lower resolution, correction will only take into account the appropriate
most significant bits.
S/H are gain-calibrated during production, but to take advantage of this the calibration value
must be read from the factory page in flash and written to the Sample and Hold Gain Calibration
(GAIN0 and GAIN1) fields of the SHCAL register.
There are 2 window monitors that allow to compare two of the result registers to some pre-
defined threshold values. The Window Mode (WM) field in WCFGy register (see
allows the user to configure operating mode in order to generate interrupts. The High Threshold
(HT) and Low Threshold (LT) fields in WCFGy register give the threshold voltage values of the
comparators. The result register to monitor is selected by the Source (SRC) field in WCFGy
register.
Table 36-10. Window Modes
Note: Comparisons are performed regardless with the HWLA setting (half word left adjust).
In dual sequencer mode, SEQ0 has priority over SEQ 1. Due to the ADC pipeline topology, the
arbiter is implemented in order to allocate optimal time slots to each sequencer in order to pipe
requests. When all analog voltages have been taken into account in the ADC pipeline, an other
sequencer can drive the analog blocs without waiting for the end of the whole conversion pro-
cess. The ADC result will be sampled by another process when getting the wanted precision.
0
0
0
0
1
1
1
1
WM
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Modes
No window mode (default)
Mode 1: active when result < HT
Mode 2: active when result > LT
Mode 3: active when LT < result < HT
Mode 4: active when result >= LT or result >= HT
reserved
reserved
reserved
AT32UC3C
Table
36-10)
1115