AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 975

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

33.6.2.6
Figure 33-9. Fault Protection
9166C–AVR-08/11
fault input 0
fault input 1
fault input y
Fault Protection
Glitch
Filter
Glitch
Filter
FFIL0
FFIL1
0
1
0
1
5 inputs provide fault protection which can force any of the PWM output pair to a programmable
value. This mechanism has priority over output overriding.
The polarity level of the faults inputs are configured by the FPOL field in the
ter” on page 1019
The fault inputs can be glitch filtered or not in function of the FFIL field in the FMR register.
When the filter is enabled, glitches on fault inputs with a width inferior to the PWM internal clock
(CCK) period are rejected.
A fault becomes active as soon as its corresponding fault input has a transition to the pro-
grammed polarity level. If the corresponding FMOD bit is written to zero in the FMR register, the
fault remains active as long as the fault input is at this polarity level. If the corresponding bit
FMOD is written to one, the fault remains active until the fault input is not at this polarity level
anymore AND until it is cleared by writing the corresponding FCLR bit in the
ter” on page 1021
can read the current level of the fault inputs thanks to the FIV field, and can know which fault is
currently active thanks to the FS field.
Each fault can be taken into account or not by the fault protection mechanism in each channel.
To be taken into account in the channel x, the fault y must be enabled by the FPEx[y] bit in the
“PWM Fault Protection Enable Registers” (FPE1). However the synchronous channels (see
Section 33.6.2.7 on page
(FPE0[y] bits).
The fault protection on a channel is triggered when this channel is enabled AND when any one
of the faults that are enabled for this channel is active. It can be triggered even if the PWM inter-
nal clock (CCK) is not running but only by a fault input that is not glitch filtered.
When the fault protection is triggered on a channel, the fault protection mechanism forces the
channel outputs to the values defined by the FPVHx and FPVLx fields in the
Value Register” on page 1022
put forcing is made asynchronously to the channel counter.
CAUTION:
FIV0
FIV1
FPOL0
FPOL1
=
=
FMOD0
FMOD1
(FMR).
(FSCR). By reading the
Write FCLR0 at 1
Write FCLR1 at 1
977) don’t use their own fault enable bits, but those of the channel 0
SET
CLR
SET
CLR
OUT
OUT
(FPV) and leads to a reset of the counter of this channel. The out-
FMOD0
FMOD1
0
1
0
1
Fault 0 Status
FS0
Fault 1 Status
FS1
”Fault Status ReSister” on page 1020
FPEx[1]
FPEx[0]
FPE0[1]
FPE0[0]
SYNCx
SYNCx
0
1
0
1
from fault 0
from fault 1
from fault y
From Output
From Output
Override
Override
FPVHx
FPVLx
OOHx
OOLx
AT32UC3C
”Fault Mode Regis-
”Fault Clear Regis-
”Fault Protection
Fault protection
(FSR), the user
channel x
on PWM
0
1
1
0
PWMHx
PWMLx
975