AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 333

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

18.6.7.4
Figure 18-29. NWAIT Latency
9166C–AVR-08/11
nternally synchronized
NWAIT signal
A[AD_MSB:2]
NBS0, NBS1,
CLK_SMC
A0, A1
NWAIT
NWAIT latency and read/write timings
NRD
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the two cycles of resynchronization
plus one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the
NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated
on
When the MODE.EXNWMODE field is enabled (ready or frozen), the user must program a pulse
length of the read and write controlling signal of at least:
Figure 18-29 on page
4
minimal pulse length
NWAIT latency 2 cycle resynchronization
3
Minimal pulse length
333.
2
EXNWMODE = 2 or 3
READMODE = 1 (NRD controlled)
NRDPULSE = 5
=
Read cycle
NWAIT latency
1
0
+
2 synchronization cycles
0
Wait STATE
0
AT32UC3C
+
1 cycle
333