AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 956

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

• RAMACERE: Ram Access Error Interrupt Enable
• RXSTALLDE: Received STALLed Interrupt Enable
• CRCERRE: CRC Error Interrupt Enable
• ERRORFIE: Errorflow Interrupt Enable
• NAKEDE: NAKed Interrupt Enable
• PERRE: Pipe Error Interrupt Enable
• TXSTPE: Transmitted SETUP Interrupt Enable
• TXOUTE: Transmitted OUT Data Interrupt Enable
• RXINE: Received IN Data Interrupt Enable
9166C–AVR-08/11
This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt
(RXSTALLDE).
This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE).
This bit is cleared when the CRCERREC bit is written to one. This will disable the Transmitted IN Data interrupt (CRCERRE).
This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE).
This bit is cleared when the ERRORFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (OVERFIE).
This bit is set when the ERRORFIES bit is written to one. This will enable the Transmitted IN Data interrupt (OVERFIE).
This bit is cleared when the NAKEDEC bit is written to one. This will disable the Transmitted IN Data interrupt (NAKEDE).
This bit is set when the NAKEDES bit is written to one. This will enable the Transmitted IN Data interrupt (NAKEDE).
This bit is cleared when the PERREC bit is written to one. This will disable the Transmitted IN Data interrupt (PERRE).
This bit is set when the PERRES bit is written to one. This will enable the Transmitted IN Data interrupt (PERRE).
This bit is cleared when the TXSTPEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXSTPE).
This bit is set when the TXSTPES bit is written to one. This will enable the Transmitted IN Data interrupt (TXSTPE).
This bit is cleared when the TXOUTEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXOUTE).
This bit is set when the TXOUTES bit is written to one. This will enable the Transmitted IN Data interrupt (TXOUTE).
This bit is cleared when the RXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXINE).
This bit is set when the RXINES bit is written to one. This will enable the Transmitted IN Data interrupt (RXINE).
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