AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 427
AT32UC3C1512C Automotive
Manufacturer Part Number
AT32UC3C1512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
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21.7.13
Name:
Access Type:
Offset:
Reset Value:
• BSWP: Byte Swap
• L: Last Descriptor in Chain
• V: Descriptor Valid
• TCIE: Transfer Complete Interrupt Enable
• BURST: Transfer Burst Size
9166C–AVR-08/11
31
23
15
7
-
-
Allows swapping of the transferred bytes, see
contains the bytes {a, b, c, d}. The following will be put into the FIFO for transmission:
0: {a, b, c, d}
1: {d, c, b, a}
2: {c, d, a, b}
3: {b, a, d, c}
Used only if the channel is in Descriptor Mode.
0: The descriptor read in is not the last descriptor in the chain. The next descriptor to be read is located at the address of the
previously read descriptor + 4 words.
1: The descriptor read in is the last descriptor in the chain. The next descriptor to be read is located at the address in the
Descriptor Start Address Register (DSARx) for the channel.
Used only if the channel is in Descriptor Mode.
0: The descriptor read in is not valid.
1: The descriptor read in is valid.
0: Transfer Complete does not set the ISR.CHxC bit.
1: Transfer Complete sets the ISR.CHxC bit.
Indicates the size of the burst used for data transfer. The MDMA will always try to use this burst size to perform transfers, but
may be forced to use smaller sizes since the transfer count may not be perfectly divisible by the transfer data size.
0: Single transfer
1: 4-beat burst
2: 8-beat burst
3: 16-beat burst
Channel Control Register x
30
22
14
L
6
-
CCR0, CCR1, CCR2, CCR3
Read/Write
0x4C, 0x5C, 0x6C, 0x7C
0x000000000
29
21
13
V
5
-
Section
TCIE
28
20
12
4
-
TCNT[15:8]
TCNT[7:0]
21.4.2. Assuming the word output from the zero-extension module
27
19
11
3
-
BURST
26
18
10
2
-
25
17
9
1
AT32UC3C
BSWP
SIZE
24
16
8
0
427
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