AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 258

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

15.5
15.5.1
9166C–AVR-08/11
Flash Commands
Write/Erase Page Operation
The FLASHC offers a command set to manage programming of the flash memory, locking and
unlocking of regions, and full flash erasing. See
To run a command, the field CMD of the Flash Command Register (FCMD) has to be written
with the command number. As soon as the FCMD register is written, the FRDY bit is automati-
cally cleared. Once the current command is complete, the FRDY bit is automatically set. If an
interrupt has been enabled by writing a one to FCR.FRDY, the interrupt request line of the Flash
Controller is activated. All flash commands except for Quick Page Read (QPR) will generate an
interrupt request upon completion if FRDY is written to one.
Any HSB bus transfers attempting to read flash memory when the FLASHC is busy executing a
flash command will be stalled, and allowed to continue when the flash command is complete.
After a command has been written to FCMD, the programming algorithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash will be busy. The waiting can be performed either by poll-
ing the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command
written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHC is
IDLE. The user must make sure that the access pattern to the FLASHC HSB interface contains
an IDLE cycle so that the command is allowed to start. Make sure that no bus masters such as
DMA controllers are performing endless burst transfers from the flash. Also, make sure that the
CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter
sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will
result in an access pattern with IDLE HSB cycles.
All the commands are protected by the same keyword, which has to be written in the eight high-
est bits of the FCMD register. Writing FCMD with data that does not contain the correct key
and/or with an invalid command has no effect on the flash memory; however, the PROGE bit is
set in the Flash Status Register (FSR). This bit is automatically cleared by a read access to the
FSR register.
Writing a command to FCMD while another command is being executed has no effect on the
flash memory; however, the PROGE bit is set in the Flash Status Register (FSR). This bit is
automatically cleared by a read access to the FSR register.
If the current command writes or erases a page in a locked region, or a page protected by the
BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE bit is
set in the FSR register. This bit is automatically cleared by a read access to the FSR register.
Flash technology requires that an erase must be done before programming. The entire flash can
be erased by an Erase All command. Alternatively, pages can be individually erased by the
Erase Page command.
The User page can be written and erased using the mechanisms described in this chapter.
1. Clear page buffer
2. Write to the page buffer the result of the logical bitwise AND operation between the
3. Write Page.
contents of the flash page and the new data to write. Only bits that were in an erased
state can be changed from the original page.
Section 15.8.2
for a complete list of commands.
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