AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 1114

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

36.6.14
36.6.15
36.6.16
36.6.16.1
9166C–AVR-08/11
Internal Timer
Peripheral DMA
Calibration
ADC gain error calibration
The sources must be configured through the Trigger Selection (TRGSEL) field of the
SEQCFGxregister. Selecting the event controller source allows any event controller source to
generate SOC.
The ADC can serve a maximum of one SOC per ADC clock cycle. Extra SOC will be ignored
and the Missed Start-Of-Conversion (MSOCx) bit in the SR register will be set. If the SOC fre-
quency provided by the event controller exceeds the ADC capability, the event controller will
generate an underrun status.
The ADCIFA embeds an internal timer used as a trigger source for SEQ0, SEQ1 and TSSEQ
which can be configured by setting the ITMC fields of the ITIMER register.
Internal Timer Trigger Period= (ITMC+1)*T(CkADC)
The 17 bits counter allows SOC period up to 174ms when CkADC clock frequency is set to
1.5 MHz.
Once set as a SOC source, the internal timer as to be started by writing a '1' in the Internal Timer
Start (TSTART) bit of the CR register. It can be stopped in the same way by writing a '1' in the
TSTOP bit of the CR register. The current status of the internal timer can be read from the Run-
ning timer status (RUN) field of the SR register: 0 means stopped, 1 means running. In addition
when the internal timer is running, if ITIMER register is written to change its frequency, the inter-
nal counter is cleared to avoid rollover phenomena.
Note: It is possible to generate an internal timer event each CkADC time slot by writing 0x0 to
the ITIMER register ITMC field and by selecting the internal timer as a SOC source.
There are two Peripheral DMA Controller (PDC) channels corresponding to the maximum num-
ber of sequencers that can be run at the same time. The Sequencer x Last Converted Value
(LCVx) register contains the last converted value of the sequencer x according to the conversion
result format. The LCV register is updated each time the sequencer ends a conversion.
If the last converted value has not been read when a new one is available, the previous data is
overwritten. This overrun status is signalled by the Sequencer x Last Converted Value Overrun
(LOVRx) bit in the SR register indicating that at least one overrun error occurred concerning
sequencer x.
The OVRx and LOVRx bits of the SR register are cleared by writing a ‘1’ respectively in the
OVRx and LOVRx fields of the SCR register.
Note: PDC transfers are 16 bits wide.
Accuracy of the conversion is based on calibration of switched capacitors and operational ampli-
fiers offset cancellation. Gain correction is done by writing a calibration word into the ADCCAL
and SHCAL registers since it is temperature and operating voltage independent.
The ADC is gain-calibrated during production, but to take advantage of this the calibration value
must be read from the factory page in flash and written to the Gain Calibration (GCAL) field of
the ADCCAL register.
AT32UC3C
1114