AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 326

• Manufacturer Part Number: AT32UC3C1512C Automotive
• Manufacturer: Atmel Corporation

18.6.6.2
Figure 18-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins
18.6.6.3
9166C–AVR-08/11
A[AD_MSB:2]
CLK_SMC
D[15:0]
NCS0
NWE
NRD
TDF optimization enabled (MODE.TDFMODE = 1)
TDF optimization disabled (MODE.TDFMODE = 0)
Read access on NCS0 (NRD controlled)
When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to
insert.
Figure 18-21 on page 326
controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRDHOLD = 4; READMODE = 1 (NRD controlled)
NWESETUP = 3; WRITEMODE = 1 (NWE controlled)
TDFCYCLES = 6; TDFMODE = 1 (optimization enabled).
When optimization is disabled, data float wait states are inserted at the end of the read transfer,
so that the data float period is ended when the second access begins. If the hold period of the
read1 controlling signal overlaps the data float period, no additional data float wait states will be
inserted.
Figure 18-22 on page
the cases:
• read access followed by a read access on another chip select.
• read access followed by a write access on another chip select.
NRDHOLD = 4
327,
TDFCYCLES = 6
shows a read access controlled by NRD, followed by a write access
Figure 18-23 on page 327
Read to Write
Wait State
NWESETUP = 3
Write access on NCS0 (NWE controlled)
and
Figure 18-24 on page 328
AT32UC3C
illustrate
326