MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 117

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MC9S12P32CFT

Manufacturer Part Number
MC9S12P32CFT
Description
MCU 16BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12P32CFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Package
48QFN EP
Family Name
HCS12
Maximum Speed
32 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/SCI/SPI
On-chip Adc
10-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.5
Each memory can be implemented in its maximum allowed size. But some devices have been defined for
smaller sizes, which means less implemented pages. All non implemented pages are called unimplemented
areas.
3.5.0.1
The global memory spaces reserved for the internal resources (RAM, D-Flash, and P-Flash) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the SoC Guide for further details.
and
spaces have fixed top addresses.
In single-chip modes accesses by the CPU12 (except for firmware commands) to any of the
unimplemented areas (see
to the unimplemented areas are allowed but the data will be undefined.
No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM
module (Refer to BDM Block Guide).
Freescale Semiconductor
Table 3-8
1. RAMSIZE is the hexadecimal value of RAM SIZE in bytes
2. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes
Registers has a fixed size of 1KB, accessible via xbus0.
SRAM has a maximum size of 11KB, accessible via xbus0.
D-Flash has a fixed size of 4KB accessible via xbus0.
P-Flash has a maximum size of 224KB, accessible via xbus0.
NVM resources (IFR) including D-Flash have maximum size of 16KB (PPAGE 0x01).
Implemented Memory in the System Memory Architecture
Implemented Memory Map
Internal Resource
show the memory spaces occupied by the on-chip resources. Please note that the memory
System RAM
Registers
D-Flash
P-Flash
Figure
Table 3-8. Global Implemented Memory Space
3-11) will result in an illegal access reset (system reset). BDM accesses
S12P-Family Reference Manual, Rev. 1.13
0x4_0000 minus FLASHSIZE
0x0_4000 minus RAMSIZE
Bottom Address
RAM_LOW =
PF_LOW =
0x0_0000
0x0_4400
(1)
(2)
Memory Map Control (S12PMMCV1)
Top Address
0x3_FFFF
0x0_03FF
0x0_3FFF
0x0_53FF
Figure 3-11
117

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