MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 512

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
A.2
This section describes the characteristics of the analog-to-digital converter.
A.2.1
The
The following constraints exist to obtain full-scale, full range results:
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
3. The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
512
Conditions are: VDDR=5.5V, RTI and COP and API enabled, see Table A-8.
Conditions are shown in
Num C
Num
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
1
2
3
4
5
6
7
8
1
2
3
Table A-14
D Reference potential
D Voltage difference V
D Voltage difference V
C Differential reference voltage
C ATD Clock Frequency (derived from bus clock via the
D ADC conversion in stop, recovery time
D
P ATD Clock Frequency in Stop mode (internal generated
V
C
C
C
C
SSA
prescaler bus)
temperature and voltage dependent clock, ICLK)
ATD Conversion Period
12 bit resolution:
10 bit resolution:
8 bit resolution:
ATD Characteristics
150°C
-40°C
25°C
ATD Operating Characteristics
Low
High
≤ V
and
RL
Table A-15
≤ V
Table A-4
IN
DDX
SSX
≤ V
Table A-13. Pseudo Stop Current Characteristics
(3)
unless otherwise noted, supply voltage 3.13 V < V
to V
to V
Rating
Rating
RH
Table A-14. ATD Operating Characteristics
show conditions under which the ATD operates.
SSA
DDA
(1)
S12P-Family Reference Manual, Rev. 1.13
≤ V
DDA
(2)
.
t
Symbol
ATDSTPRC
N
N
V
Symbol
N
f
I
I
I
∆
∆
ATDCLk
DDPS
DDPS
DDPS
RH
CONV12
CONV10
CONV8
V
V
VDDX
VSSX
RH
V
RL
-V
RL
V
–2.35
Min
V
–0.1
3.13
0.25
DDA
Min
DDA
0.6
20
19
17
SSA
—
/2
< 5.5 V
Typ
450
175
200
Typ
5.0
—
—
—
0
0
1
Freescale Semiconductor
V
V
Max
Max
DDA
0.1
0.1
5.5
8.0
1.7
1.5
42
41
39
DDA
/2
Cycles
clock
Unit
MHz
MHz
Unit
ATD
µA
µA
µA
us
V
V
V
V
V