MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 220

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.12
This register is used to restart the COP time-out period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
7.3.2.13
The CPMUHTCTL register configures the temperature sense features.
Read: Anytime
Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only
220
0x02F0
0x003F
Reset
Reset
W
W
R
R
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
Bit 7
S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)
H
0
0
0
0
7
7
igh
T
= Unimplemented or Reserved
emperature
Bit 6
0
0
0
0
6
6
Figure 7-15. S12CPMU CPMUARMCOP Register
S12P-Family Reference Manual, Rev. 1.13
VSEL
Bit 5
0
0
0
5
5
Control Register (CPMUHTCTL)
Bit 4
0
0
0
0
4
4
Bit 3
HTE
0
0
0
3
3
HTDS
Bit 2
0
0
0
2
2
Freescale Semiconductor
HTIE
Bit 1
0
0
0
1
1
HTIF
Bit 0
0
0
0
0
0