MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 44

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Overview MC9S12P-Family
1.9.2
The MC9S12P has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description
refer to S12CPMU section.
1.10
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 13.5 Security
1.11
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.11.1
Table 1-11. lists all Reset sources and the vector locations. Resets are explained in detail in the Section
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU)
1.11.2
Table 1-12
Section Chapter 4 Interrupt Module (S12SINTV1)) provides an interrupt vector base register (IVBR)
to relocate the vectors.
44
Vector Address
Vector base + $F8
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector Address
Security
Resets and Interrupts
lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Low Power Operation
Resets
Interrupt Vectors
$FFFC
$FFFE
$FFFE
$FFFE
$FFFE
$FFFA
(1)
Unimplemented instruction trap
Table 1-12. Interrupt Vector Locations (Sheet 1 of 3)
Interrupt Source
Table 1-11. Reset Sources and Vector Locations
XIRQ
SWI
IRQ
Low Voltage Reset (LVR)
S12P-Family Reference Manual, Rev. 1.13
Power-On Reset (POR)
Illegal Address Reset
COP watchdog reset
External pin RESET
Clock monitor reset
Reset Source
Mask
None
None
CCR
X Bit
I bit
Mask
None
None
None
None
None
None
IRQCR (IRQEN)
CCR
Local Enable
None
None
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
Local Enable
None
None
None
None
Freescale Semiconductor
from STOP
Wake up
Yes
Yes
-
-
from WAIT
Wakeup
Yes
Yes
-
-