MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 335

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3.2.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
An exception to this is when channels are concatenated. After concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low-order PWMEx bit. In this case, the high-order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all six PWM channels are disabled (PWME5–PWME0 = 0), the prescaler counter
shuts off for power savings.
Read: anytime
Write: anytime
Freescale Semiconductor
Module Base + 0x0000
PWME5
PWME4
PWME3
PWME2
Reset
Field
5
4
3
2
W
R
Pulse Width Channel 5 Enable
0 Pulse width channel 5 is disabled.
1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM,output bit 5 when
Pulse Width Channel 4 Enable
0 Pulse width channel 4 is disabled.
1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when
Pulse Width Channel 3 Enable
0 Pulse width channel 3 is disabled.
1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when
Pulse Width Channel 2 Enable
0 Pulse width channel 2 is disabled.
1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when
PWM Enable Register (PWME)
0
0
7
its clock source begins its next cycle.
its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output line 4 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled.
The first PWM cycle after enabling the channel can be irregular.
= Unimplemented or Reserved
0
0
6
Figure 10-3. PWM Enable Register (PWME)
S12P-Family Reference Manual, Rev. 1.13
Table 10-2. PWME Field Descriptions
PWME5
0
5
PWME4
NOTE
0
4
Description
PWME3
Pulse-Width Modulator (PWM8B6CV1) Block Description
0
3
PWME2
0
2
PWME1
0
1
PWME0
0
0
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