MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 19

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.3
The following sections provide more details of the modules implemented on the MC9S12P family.
1.3.1
S12 CPU is a high-speed 16-bit processing unit:
1.3.2
On-chip flash memory on the MC9S12P features the following:
Freescale Semiconductor
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Pulse width modulation (PWM) module with 6 x 8-bit channels
10-channel, 12-bit resolution successive approximation analog-to-digital converter (ATD)
One serial peripheral interface (SPI) module
One serial communication interface (SCI) module supporting LIN communications
One multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Autonomous periodic interrupt (API)
Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
Includes many single-byte instructions. This allows much more efficient use of ROM space.
Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
Up to 128 Kbyte of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
4 Kbyte data flash space
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
— Erase sector size 256 bytes
— Automated program and erase algorithm
— User margin level setting for reads
Module Features
and double fault detection
and double fault detection
S12 16-Bit Central Processor Unit (CPU)
On-Chip Flash with ECC
S12P-Family Reference Manual, Rev. 1.13
Device Overview MC9S12P-Family
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