MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 93

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
1. Read: Anytime
2.3.50
2.3.51
Freescale Semiconductor
Address 0x0269
Address 0x026A
7-6, 2-0
7-6, 2-0
Write:Never, writes to this register have no effect.
Write: Anytime
DDRJ
Field
Field
PTIJ
Reset
Reset
W
W
R
R
Port J input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port J data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
DDRJ7
PTIJ7
Port J Input Register (PTIJ)
Port J Data Direction Register (DDRJ)
u
0
7
7
= Unimplemented or Reserved
DDRJ6
PTIJ6
u
0
6
6
Figure 2-49. Port J Data Direction Register (DDRJ)
Table 2-45. DDRJ Register Field Descriptions
Table 2-44. PTIJ Register Field Descriptions
Figure 2-48. Port J Input Register (PTIJ)
S12P-Family Reference Manual, Rev. 1.13
5
0
u
5
0
0
0
u
0
0
4
4
Description
Description
u = Unaffected by reset
0
u
0
0
3
3
DDRJ2
PTIJ2
u
0
2
2
Port Integration Module (S12PPIMV1)
Access: User read/write
DDRJ1
PTIJ1
u
0
1
1
Access: User read
DDRJ0
PTIJ0
u
0
0
0
93
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