MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 340

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulse-Width Modulator (PWM8B6CV1) Block Description
Read: anytime
Write: anytime
10.3.2.6
The PWMCTL register provides for various control of the PWM module.
340
Module Base + 0x0004
Reset
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
Field
5
4
3
2
1
0
W
R
Center Aligned Output Mode on Channel 5
0 Channel 5 operates in left aligned output mode.
1 Channel 5 operates in center aligned output mode.
Center Aligned Output Mode on Channel 4
0 Channel 4 operates in left aligned output mode.
1 Channel 4 operates in center aligned output mode.
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.
PWM Control Register (PWMCTL)
0
0
7
Write these bits only when the corresponding channel is disabled.
= Unimplemented or Reserved
Figure 10-7. PWM Center Align Enable Register (PWMCAE)
0
0
6
Table 10-8. PWMCAE Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
CAE5
0
5
CAE4
NOTE
0
4
Description
CAE3
0
3
CAE2
0
2
Freescale Semiconductor
CAE1
0
1
CAE0
0
0