MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 211

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.6
This register controls S12CPMU clock selection.
Read: Anytime
Write:
Freescale Semiconductor
0x0039
PLLSEL
Reset
PSTP
1. Only possible when PROT=0 (CPMUPROT register).
2. All bits anytime in Special Modes.
3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: Anytime in Normal Mode.
4. COPOSCSEL: Anytime in normal mode until CPMUCOP write once has taken place.
Field
7
6
W
R
PLLSEL
If COPOSCSEL was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL=1
or insufficient OSCCLK quality), then COPOSCSEL can be set once again.
PLL Select Bit
This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock).
PLLSEL can only be set to 0, if UPOSC=1.
UPOSC= 0 sets the PLLSEL bit.
Entering Full Stop Mode sets the PLLSEL bit.
0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, f
1 System clocks are derived from PLLCLK, f
Pseudo Stop Bit
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode (Full Stop Mode).
1 Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP.
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
S12CPMU Clock Select Register (CPMUCLKS)
1
7
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL and COPOSCSEL was successful.
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
Mode with OSCE bit is already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator t
= Unimplemented or Reserved
PSTP
Figure 7-9. S12CPMU Clock Select Register (CPMUCLKS)
0
6
S12P-Family Reference Manual, Rev. 1.13
Table 7-5. CPMUCLKS Descriptions
0
0
5
UPOSC
before entering Pseudo Stop Mode.
bus
0
0
4
= f
Description
PLL
/ 2.
S12 Clock, Reset and Power Management Unit (S12CPMU)
PRE
0
3
PCE
0
2
bus
= f
osc
/ 2.
OSCSEL
RTI
0
1
OSCSEL
COP
0
0
211