MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 55

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Write access not applicable for one or more register bits. Refer to register description.
2. Refer to device memory map to determine related module.
3. Mode dependent.
4. Read always returns logic level on pins.
Freescale Semiconductor
Port
AD
Register
J
PORTB
0x0000
PORTA
0x0001
0x0002
0x0003
Name
DDRA
DDRB
Offset or
Address
0x026A
0x026B
0x026C
0x026D
0x026E
0x0268
0x0269
0x026F
0x0270
0x0271
0x0272
0x0273
0x0274
0x0275
0x0276
0x0277
0x0278
0x027F
:
W
W
W
W
R
R
R
R
DDRA7
DDRB7
PTJ—Port J Data Register
PTIJ—Port J Input Register
DDRJ—Port J Data Direction Register
RDRJ—Port J Reduced Drive Register
PERJ—Port J Pull Device Enable Register
PPSJ—Port J Polarity Select Register
PIEJ—Port J Interrupt Enable Register
PIFJ—Port J Interrupt Flag Register
PT0AD—Port AD Data Register
PT1AD—Port AD Data Register
DDR0AD—Port AD Data Direction Register
DDR1AD—Port AD Data Direction Register
RDR0AD—Port AD Reduced Drive Register
RDR1AD—Port AD Reduced Drive Register
PER0AD—Port AD Pull Up Enable Register
PER1AD—Port AD Pull Up Enable Register
PIM Reserved
Bit 7
PB7
PA7
= Unimplemented or Reserved
DDRA6
DDRB6
PB6
PA6
6
Table 2-2. Block Memory Map (continued)
S12P-Family Reference Manual, Rev. 1.13
DDRA5
DDRB5
Register
PB5
PA5
5
DDRA4
DDRB4
PB4
PA4
4
DDRA3
DDRB3
PB3
PA3
3
Access Reset Value
DDRA2
DDRB2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PB2
R
R
R
R
R
R
PA2
2
Port Integration Module (S12PPIMV1)
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DDRA1
DDRB1
4
PA1
PB1
1
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DDRA0
DDRB0
Bit 0
PB0
PA0
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