MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 164

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12S Debug Module (S12SDBGV2)
6.3.2.7
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
164
CNT[5:0]
Field
TBF
5–0
7
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGSR[7]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer.
Table 6-13
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-
trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register
is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur
during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer
entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace
buffer.
Debug State Control Registers
TBF
0
0
1
1
shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
Table 6-14. State Control Register Access Encoding
CNT[5:0]
000000
000001
000010
000100
000110
111111
000000
000001
111110
COMRV
..
..
..
00
01
10
11
Table 6-12. DBGCNT Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Table 6-13. CNT Decoding Table
ARM bit will be cleared and the tracing session ends.
oldest data has been overwritten by most recent data
Visible State Control Register
64 lines valid; if using Begin trigger alignment,
Description
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
64 lines valid,
No data valid
63 lines valid
Description
2 lines valid
4 lines valid
6 lines valid
1 line valid
..
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