MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 337

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3.2.3
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Read: anytime
Write: anytime
Freescale Semiconductor
Module Base + 0x0002
PPOL3
PPOL2
PPOL1
PPOL0
Reset
Field
3
2
1
0
W
R
Pulse Width Channel 3 Polarity
0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 2 Polarity
0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 1 Polarity
0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 0 Polarity
0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached.
PWM Clock Select Register (PWMCLK)
0
0
7
Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
= Unimplemented or Reserved
0
0
6
Table 10-3. PWMPOL Field Descriptions (continued)
Figure 10-5. PWM Clock Select Register (PWMCLK)
S12P-Family Reference Manual, Rev. 1.13
PCLK5
0
5
PCLK4
NOTE
0
4
Description
PCLK3
Pulse-Width Modulator (PWM8B6CV1) Block Description
0
3
PCLK2
0
2
PCLK1
0
1
PCLK0
0
0
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