MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 89

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
2.3.43
Freescale Semiconductor
Address 0x025B
Write: Anytime
DDRP
DDRP
RDRP
Field
Field
7,5-0
Reset
4-0
5
W
R
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. If the emergency shut-down feature is enabled
this pin is an input. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port P reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
RDRP7
Port P Reduced Drive Register (RDRP)
0
7
Table 2-37. DDRP Register Field Descriptions (continued)
0
0
6
Figure 2-41. Port P Reduced Drive Register (RDRP)
Table 2-38. RDRP Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
RDRP5
5
0
RDRP4
0
4
Description
Description
RDRP3
0
3
RDRP2
0
2
Port Integration Module (S12PPIMV1)
Access: User read/write
RDRP1
0
1
RDRP0
0
0
89
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