MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 194

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12S Debug Module (S12SDBGV2)
6.5.10
Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed
again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing
the SCR2 encoding as shown in red this scenario becomes possible.
6.5.11
Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1.
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one
or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger
is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third
consecutive occurrence of event M0 without a reset M1.
Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point
in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before
M1 then a trigger is generated.
194
SCR1=0010
SCR1=0010
State1
State1
Scenario 9
Scenario 10
SCR1=0111
State1
M1
M2
M2
SCR2=0100
SCR2=0011
State2
State2
M01
M2
S12P-Family Reference Manual, Rev. 1.13
M1
M0
Figure 6-40. Scenario 10a
Figure 6-41. Scenario 10b
SCR2=1111
Figure 6-39. Scenario 9
State2
M2
M1
SCR3=0010
SCR3=0000
M01
State3
State3
Final State
M0
M0
Final State
Final State
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