MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 323

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2.11
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
9.3.2.12
The A/D conversion results are stored in 10 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL3.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Attention, n is the conversion number, NOT the channel number!
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x000E
CMPHT[9:0]
Reset
Field
9–0
W
R
15
0
0
ATD Compare Higher Than Register (ATDCMPHT)
ATD Conversion Result Registers (ATDDRn)
Compare Operation Higher Than Enable for conversion number n (n= 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a
Sequence (n conversion number, NOT channel number!) — This bit selects the operator for comparison of
conversion results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
= Unimplemented or Reserved
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
14
0
0
Figure 9-13. ATD Compare Higher Than Register (ATDCMPHT)
13
0
0
12
0
0
Table 9-20. ATDCMPHT Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
11
0
0
10
0
0
9
0
NOTE
0
8
Description
0
7
0
6
CMPHT[9:0]
5
0
Analog-to-Digital Converter (ADC12B10C)
0
4
0
3
0
2
0
1
0
0
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