MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 305

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MC9S12P32CFT

Manufacturer Part Number
MC9S12P32CFT
Description
MCU 16BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12P32CFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Package
48QFN EP
Family Name
HCS12
Maximum Speed
32 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/SCI/SPI
On-chip Adc
10-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 9
Analog-to-Digital Converter (ADC12B10C)
Revision History
9.1
The ADC12B10C is a 10-channel, 12-bit, multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ATD accuracy.
9.1.1
Freescale Semiconductor
Number
Version
V01.00
V01.01
V01.02
V01.03
8-, 10-, or 12-bit resolution.
Conversion in Stop Mode using internally generated clock
Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value
Programmable sample time.
Left/right justified result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 10 analog input channels.
Special conversions for V
1-to-10 conversion sequence lengths.
Continuous conversion mode.
Multiple channel scans.
Introduction
14 Sept 2007
25 July 2007
1 Oct 2007
9 Oct 2007
Revision
Features
Date
14 Sept 2007
25 July 2007
1 Oct 2007
9 Oct 2007
Effective
Date
RH
S12P-Family Reference Manual, Rev. 1.13
, V
RL
Author
, (V
RL
+V
RH
Initial version
Added reserved registers at the end the memory map.
Added following mention where applies:
(n conversion number, NOT channel number!)
Modified table “Analog Input Channel Select Coding” due to
new customer feature (SPECIAL17).
)/2.
Description of Changes
305

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