MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 440

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

128 KByte Flash Module (S12FTMRC128K1V1)
13.3.2.8
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
1. The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either
13.3.2.9
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
440
MGSTAT[1:0]
single fault or double fault but never both). A simultaneous access collision (read attempted while command running) is
indicated when both SFDIF and DFDIF flags are high.
MGBUSY
Offset Module Base + 0x0007
Reset
DFDIF
SFDIF
Field
RSVD
Field
1–0
1
0
3
2
W
R
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
was attempted on a Flash block that was under a Flash command operation.
writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or an invalid Flash array read operation attempted
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or an invalid Flash array read operation attempted
Flash Error Status Register (FERSTAT)
P-Flash Protection Register (FPROT)
0
0
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Reserved Bit — This bit is reserved and always reads 0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. See
“Flash Command
7
= Unimplemented or Reserved
0
0
6
Figure 13-12. Flash Error Status Register (FERSTAT)
Description,” and
Table 13-14. FSTAT Field Descriptions (continued)
Table 13-15. FERSTAT Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
0
0
5
Section 13.6,
0
0
4
Description
Description
“Initialization” for details.
.
0
0
3
0
0
2
(1)
The DFDIF flag is cleared by
Freescale Semiconductor
DFDIF
0
1
Section 13.4.5,
SFDIF
0
0
.
1