MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 111

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Cache invalidation can be performed in the two following ways:
These invalidation operations can be initiated from the ColdFire core or the debug module.
4.5.2.3
For every memory reference generated by the processor or debug module, a set of effective attributes is
determined based on the address and the ACRs. Caching modes determine how the cache handles an
access. An access can be cacheable or cache-inhibited. For normal accesses, the ACRn[CM] bit
corresponding to the address of the access specifies the caching mode. If an address does not match an
ACR, the default caching mode is defined by CACR[DCM]. The specific algorithm is as follows:
if (address == ACR0-address including mask)
else if (address == ACR1-address including mask)
Addresses matching an ACR can also be write protected using ACR[WP].
Reset disables the cache and clears all CACR bits. Reset does not automatically invalidate cache entries;
they must be invalidated through software.
The ACRs allow CACR defaults to be overridden. In addition, some instructions (for example, CPUSHL)
and processor core operations perform accesses that have an implicit caching mode associated with them.
The following sections discuss the different caching accesses and their associated cache modes.
4.5.2.3.1
If ACRn[CM] or the default field of the CACR indicates the access is cacheable, a read access is read from
the cache if matching data is found. Otherwise, the data is read from memory and the cache is updated.
When a line is being read from memory, the longword in the line that contains the core-requested data is
loaded first and the requested data is given immediately to the processor, without waiting for the three
remaining longwords to reach the cache.
4.5.2.3.2
Memory regions can be designated as cache-inhibited, which is useful for memory containing targets such
as I/O devices and shared data structures in multiprocessing systems. Do not cache memory-mapped
registers (for example, registers shown with an MBAR offset). If the corresponding ACRn[CM] or
CACR[DCM] indicates cache-inhibited the access is cache-inhibited. The caching operation is identical
for both cache-inhibited modes, which differ only regarding recovery from an external bus error.
Freescale Semiconductor
•
•
Setting CACR[CINVA] forces the entire instruction cache to be marked as invalid. The
invalidation operation requires 64 cycles because the cache sequences through the entire tag array,
clearing a single location each cycle. Any subsequent instruction fetch accesses are postponed until
the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is
executed, the cache entry defined by bits 9–4 of the source address register is invalidated, provided
CACR[CDPI] is cleared.
effective attributes = ACR0 attributes
else effective attributes = CACR default attributes
Caching Modes
Cacheable Accesses
Cache-Inhibited Accesses
effective attributes = ACR1 attributes
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Local Memory
4-9