MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 128

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Debug Support
5.4.4
The configuration/status register (CSR) defines the debug configuration for the processor and memory
subsystem and contains status information from the breakpoint logic. CSR is write-only from the
programming model. It can be read from and written to through the BDM port. CSR is accessible in
supervisor mode as debug control register 0x00 using the WDEBUG instruction and through the BDM
port using the
Table 5-8
5-10
31–28
23–20
19–17
Bit
27
26
25
24
16
1
DRc[4–0]
Bit 7 is reserved for Freescale use and must be written as a zero.
Reset
Reset
R/W
Field
Field MAP TRC EMU
R/W R/W R/W R/W
BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. BSTAT is
Name
BKPT
HALT
describes CSR fields.
TRG
FOF
HRL
IPW
1
—
Configuration/Status Register (CSR)
RDMREG
31
15
0
cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint
is triggered and the level-2 breakpoint is disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF is cleared
whenever CSR is read.
Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and forced
entry into BDM. Reset, the debug
Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset, the debug
GO
Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset, the debug
GO
Hardware revision level. Indicates the level of debug module functionality. An emulator could use this
information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A) (this is the only valid value for the MCF5272)
Reserved, should be cleared.
Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming
model registers. IPW can be modified only by commands from the external development system.
command, or reading CSR clear HALT.
command, or reading CSR clear BKPT.
14
0
BSTAT
0000
MCF5272 ColdFire
R
and
13
0
WDMREG
Figure 5-7. Configuration/Status Register (CSR)
28
12
DDC
R/W
00
FOF TRG HALT BKPT
Table 5-8. CSR Field Descriptions
27
11
R
0
commands.
®
Integrated Microprocessor User’s Manual, Rev. 3
UHE
R/W
26
10
R
0
0
GO
25
R
command, or reading CSR clear TRG.
0
9
BTB
R/W
00
24
R
0
8
0x00
Description
—
23
R
0
7
1
NPL
R/W R/W R/W
0
6
0000
HRL
R
IPI
0
5
SSM
20
0
4
19
0
3
Freescale Semiconductor
—
—
0
0000
—
—
17
0
IPW
R/W
16
0
0