MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 132

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Debug Support
5.4.7
The TDR, shown in
with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the debug module. The
TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as a one-
or two-level trigger. TDR[31–16] define the second-level trigger and bits 15–0 define the first-level
trigger.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Table 5-14
5-14
31–30
15–14
DRc[4–0]
29/13
Bits
Reset
Reset
Field
Field
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
Name
TRC
through the BDM port using the
EBL
31
15
describes TDR fields.
—
Trigger Definition Register (TDR)
TRC
—
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR (by clearing TDR[29,13])before defining triggers.
30
14
Trigger response control. Determines how the processor responds to a completed trigger condition. The
trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Reserved, should be cleared.
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint trigger.
Clearing it disables all breakpoints at that level.
EBL
EBL
Table
29
13
MCF5272 ColdFire
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
5-11, configures the operation of the hardware breakpoint logic that corresponds
28
12
Figure 5-11. Trigger Definition Register (TDR)
27
11
Table 5-14. TDR Field Descriptions
WDMREG
®
Integrated Microprocessor User’s Manual, Rev. 3
26
10
command.
25
0000_0000_0000_0000
0000_0000_0000_0000
9
NOTE
Second-Level Trigger
24
First-Level Trigger
8
Description
0x07
23
7
22
6
DI
DI
21
5
EAI
EAI
20
4
EAR EAL EPC
EAR EAL EPC
Freescale Semiconductor
19
3
18
2
17
1
PCI
PCI
16
0