MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 223

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

stays inactive for 60 bit times. If so, the transmission begins after waiting an additional 36 bit times (96 bit
times after carrier sense originally went inactive).
If a collision occurs during the transmit frame, the FEC follows the specified backoff procedures and
attempts to retransmit the frame until the retry limit is reached. The FEC stores the first 64 bytes of the
transmit frame in internal RAM, so they need not be retrieved from system memory in case of a collision.
This improves external bus use and reduces latency whenever the backoff process results in an immediate
retransmission.
See Figure 11-28 on page 11-37 for the following discussion. When the end of the last transmit buffer in
the current frame is reached, the 32-bit frame check sum is appended (if TxBD[TC] is set) and
transmission is disabled (E_TxEN is negated). Following the transmission of the check sum, the FEC
writes the frame status bits into the buffer descriptor and clears the ready bit. When the end of the current
BD is reached but it is not the last buffer in the frame, then only the ready bit is cleared. Short frames are
automatically padded by the transmit logic.
If the transmit frame length exceeds the value programmed in the maximum frame length register, the
BABT interrupt is asserted. However, the entire frame is transmitted and is not truncated. See
Section 11.5.14, “Maximum Frame Length Register
Both buffer and frame interrupts may be generated as determined by the EIMR register settings.
Setting the graceful transmit stop bit, TCR[GTS], pauses transmission. The FEC transmitter stops
immediately if no transmission is in progress. Otherwise it continues transmission until the current frame
finishes normally or terminates with a collision. When TCR[GTS] is cleared, the FEC resumes
transmission with the next frame.
The FEC transmits bytes lsb first.
11.4.1
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC, short frame checking, and maximum frame length checking.
When the FEC receiver is enabled by setting ECR[ETHER_EN] and RDAR[24] it immediately starts
processing receive frames. Received frame processing proceeds as follows:
Freescale Semiconductor
•
•
•
•
•
•
When E_RxDV asserts, the receiver first checks for a valid header comprised of a preamble and
start-of-frame delimiter (PA/SDF).
If the PA/SFD is valid, it is stripped off and the frame processed further by the receiver. If a valid
PA/SFD is not found, the frame is ignored.
In serial mode, the first 16 bit times of E_RxD0 following assertion of E_RxDV (RENA) are
ignored.
After the first 16 bit times, the data sequence is checked for alternating I/0.
If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is
ignored.
After bit time 21, the data sequence is monitored for a valid start-of-frame delimiter (SFD) of 11.
If a 00 is detected, the frame is rejected. When a 11 is detected, the PA/SFD sequence is complete.
FEC Frame Reception
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
(MFLR).”
Ethernet Module
11-5