MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 325

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

13.5.17 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnGCIT registers are 8-bit registers containing the monitor channel bits to be transmitted for each of
the four ports on the MCF5272.
Freescale Semiconductor
31–29, 23–21,
27–24, 19–16,
28, 20, 12, 4
15–13, 7–5
11–8, 3–0
Reset
Reset
Chan
Chan
Field
Field
Addr
R/W
R/W
Bits
31
15
C3–C0 C/I bits. The CPU writes C/I data to be transmitted, on the GCI or SCIT channel 0, into these
Name
—
—
—
R
Figure 13-29. GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
MCF5272 ColdFire
MBAR + 0x378 (P0GCIT), 0x379 (P1GCIT), 0x37A (P3GCIT), 0x37B (P4GCIT)
29
13
Reserved, should be cleared.
Ready. This bit is set, by the CPU to indicate to the C/I channel controller that data is ready for
transmission. The transition of this bit from a 0 to a 1 starts the C/I state machine which responds
with the ACK bit once transmission of two successive C/I words is complete. This bit is
automatically cleared by the GCI controller when it generates a transmit acknowledge (ACK bit in
PGCITSR register). The clearing of this bit by reading this register also clears the aperiodic GCT
interrupt.
positions. The CPU must ensure that this data is not overwritten before it has been transmitted the
required minimum amount of times, that is, so any change is detected and confirmed by a receiver.
A maskable interrupt is generated when this data has been successfully transmitted
Table 13-12. P0GCIT–P3GCIT Field Descriptions
28
12
R
R
P0GCIT
P2GCIT
C3
C3
27
11
®
Integrated Microprocessor User’s Manual, Rev. 3
C2
C2
26
10
C1
0000_0000_0000_0000
C1
0000_0000_0000_0000
25
9
Read/Write
Read/Write
C0
C0
24
8
23
7
Description
—
—
21
5
Physical Layer Interface Controller (PLIC)
20
R
R
P1GCIT
P3GCIT
4
C3
C3
19
3
C2
C2
18
2
C1
C1
17
1
C0
C0
16
0
13-29