MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 183

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

7.2.6
The programmable interrupt vector register (PIVR),
controller returns in response to interrupt acknowledge cycles for the various peripherals and discrete
interrupt sources.
Pending interrupts are presented to the processor core in order of priority from highest to lowest. The core
responds to an interrupt request by initiating an interrupt acknowledge cycle to receive a vector number,
which allows the core to locate the interrupt’s service routine. The interrupt controller is able to identify
the source of the highest priority interrupt that is being acknowledged and provide the interrupt vector to
the core. The three most significant bits of the interrupt vector are programmed by the user in the PIVR.
The lower five bits are provided by the interrupt controller, depending on the source, as shown in
Table
If the core initiates an interrupt acknowledge cycle prior to the PIVR being programmed, the interrupt
controller returns the uninitialized interrupt vector (0x0F). If the core initiates an interrupt acknowledge
cycle after the PIVR has been initialized, but there is no interrupt pending, the interrupt controller returns
the user a spurious interrupt vector (0xxxx0_0000). Because the interrupt controller responds to all
interrupt acknowledges, a bus error situation cannot occur during an interrupt-acknowledge cycle.
Table 7-7
Freescale Semiconductor
Bits
7-5
4-0
7-7.
Field
—
IV
describes PIVR fields.
Programmable Interrupt Vector Register (PIVR)
Address
These bits provide the high three bits of the interrupt vector for interrupt acknowledge cycles from all sources.
To conform to the core interrupt vector allocation, these bits should be set equal to or greater than 010. See
Table
Reserved, should be cleared.
Reset
Field
R/W
2-3.
MCF5272 ColdFire
Figure 7-9. Programmable Interrupt Vector Register (PIVR)
7
IV
Table 7-7. PIVR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
5
MBAR + 0x03F
4
Figure
0000_1111
Description
R/W
7-9, specifies the vector numbers the interrupt
—
0
Interrupt Controller
7-9