MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 236

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Ethernet Module
To generate an MII management interface read frame (read a PHY register), the user must write {01 10
PHYAD REGAD 10 XXXX} to MMFR (the contents of the DATA field are a don’t care). Writing this
pattern causes the control logic to shift out the data in the MMFR register following a preamble generated
by the control state machine.The contents of the MMFR register are altered as the contents are serially
shifted, and are unpredictable if read by the user. Once the read management frame operation completes,
the MII interrupt is generated. At this time the contents of the MMFR register matches the original value
written except for the DATA field, whose contents are replaced by the value read from the PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents are altered.
Software should use the MII interrupt to avoid writing to the MMFR register while frame generation is in
progress.
11.5.8
The MSCR register,
dropping the preamble on the MII management frame and provides observability (intended for
manufacturing test) of an internal counter used in generating the E_MDC clock signal.
Table 11-14
11-18
31–8
Bits
6–1
7
0
Reset
Reset
Field
Field
Addr
R/W
R/W
DIS_PREAMBLE
31
15
MII Speed Control Register (MSCR)
MII_SPEED
describes the MSCR fields.
Name
—
—
Figure
MCF5272 ColdFire
0000_0000
Reserved, should be cleared.
Disable preamble. Asserting this bit causes the preamble of 32 consecutive 1’s not to be
prepended to the MII management frame. The MII standard allows the preamble to be dropped
if the attached PHY device(s) do not require it.
MII frequency divider. MII_SPEED controls the frequency of the MII management interface
clock (E_MDC) relative to system clock. A value of 0 in this field turns off the E_MDC and
leaves it in low-voltage state. Any non-zero value results in an E_MDC frequency given by the
following formula:
MDC_FREQUENCY = system frequency / (4 * MII_SPEED)
Reserved, should be cleared.
11-12, provides control of the MII clock (E_MDC pin) frequency, allows
—
Figure 11-12. MII Speed Control Register (MSCR)
Table 11-14. MSCR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
8
0000_0000_0000_0000
DIS_PREAMBLE
MBAR + 0x884
Read/Write
Read/Write
—
0
7
Description
6
MII_SPEED
000_000
Freescale Semiconductor
1
—
16
0
0