MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 471

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

20.12.2 Normal Reset
External normal resets should be performed anytime it is important to maintain the data stored in SDRAM
during a reset. An external normal reset is performed when an external device asserts RSTI while negating
DRESETEN. At power on reset both RSTI and DRESETEN must be asserted simultaneously. If
DRESETEN is not asserted at the same time as RSTI at power up, the SDRAMC cannot be initialized by
software.
During an external normal reset, RSTI must be asserted for a minimum of six CLKINs.
functional timing diagram of external normal reset operation, illustrating relationships among RSTI,
DRESETEN, RSTO, mode selects, and bus signals. RSTI and DRESETEN are internally synchronized on
consecutive falling and rising clocks before being used and must meet the specified setup and hold times
to the falling edge of CLKIN only if recognition by a specific falling edge is required
The levels of the mode select inputs, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, QSPI_CS0/BUSW0, and
HiZ are sampled when RSTO negates and they select the port size of CS0 and the physical data bus width
after a master reset occurs. RSTO is asserted as long as RSTI is asserted and remains asserted for 32,768
CLKIN cycles after RSTI is negated. For proper normal reset operation, DRESETEN must be negated as
long as RSTI is asserted.
The levels of the mode select inputs, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, and QSPI_CS0/BUSW0,
are sampled when RSTO negates and they select the port size of CS0 and the physical data bus width after
a master reset occurs. The INTx signals are synchronized and are registered on the last falling edge of
CLKIN where RSTI is asserted.
During the normal reset period, all outputs are driven to their default levels. Once RSTO negates, all bus
signals continue to remain in this state until the ColdFire core begins the first bus cycle for reset exception
processing.
Freescale Semiconductor
.
CLKIN
VDD
RSTI
DRESETEN
Mode Select
Inputs
RSTO
BUS SIGNALS
MCF5272 ColdFire
(H)
Figure 20-22. Normal Reset Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
CLK CYCLES
T >= 6
CLK CYCLES
T = 32,768
CLK CYCLES
T >= 22
Figure 20-22
Bus Operation
20-23
is a