MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 385

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

The receiver detects the beginning of a break in the middle of a character if the break persists through the
next character time. If the break begins in the middle of a character, the receiver places the damaged
character in the Rx FIFO stack and sets the corresponding USRn error bits and USRn[RxRDY]. Then, if
the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and
sets USRn[RB,RxRDY].
16.5.2.3
Whenever the CPU writes a character for transmission into UTB, the character is placed into the 24-byte
transmitter FIFO. UTB fills the last spot in the FIFO and holds the last character to be transmitted.
Visibility into the status of the FIFO is provided by various bits and interrupts, as shown in
16.5.2.4
The FIFO stack is used in the UART’s receiver buffer logic. The FIFO is 24 bytes deep. The receive buffer
consists of the FIFO and a receiver shift register connected to the RxD (see
assembled in the receiver shift register and loaded into the top empty receiver holding register position of
the FIFO. Similar to the transmitter, several status bits and interrupts provide visibility into the status of
the FIFO.
In addition to the data byte, three status bits, parity error (PE), framing error (FE), and received break (RB),
are appended to each data character in the FIFO; OE (overrun error) is not appended. By programming the
ERR bit in the channel’s mode register (UMR1n), status is provided in character or block modes.
USRn[RxRDY] is set when at least one character is available to be read by the CPU. A read of the receiver
buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top
of the FIFO stack and its associated status bits are popped and the receiver shift register can add new data
at the bottom of the stack. The FIFO-full status bit (FFULL) is set if all 24 stack positions are filled with
data. Either the RxRDY or FFULL bit can be selected to cause an interrupt.
The two error modes are selected by UMR1n[ERR] as follows:
Freescale Semiconductor
USR[TxEMP] = 1
USR[TxRDY] = 1
USR[FFULL] = 1
UTF[TXS]
UTF[TXB]
•
•
Status Bit
In character mode (UMR1n[ERR] = 0), status is given in the USRn for the character at the top of
the FIFO.
In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO stack
since the last
FIFO stack. Block mode offers a data-reception speed advantage where the software overhead of
error-checking each character cannot be tolerated. However, errors are not detected until the check
is performed at the end of an entire message—the faulting character in the block is not identified.
Transmitter FIFO
Receiver FIFO
The transmitter FIFO and shift register are empty and a data underrun occurred.
At least one FIFO stage is available for a character to be transmitted. If this bit is cleared, the
FIFO is full and a subsequent write to the FIFO will be ignored.
The programmed level of emptiness (UTF[TXS]) has been reached.
Indicates the level of emptiness of the transmitter FIFO
Indicates the number of characters, 0–24, in the transmitter FIFO
RESET ERROR STATUS
MCF5272 ColdFire
Table 16-16. Transmitter FIFO Status Bits
®
Integrated Microprocessor User’s Manual, Rev. 3
command. Status is updated as characters reach the top of the
Indicated Condition
Figure
16-24). Data is
Table
UART Modules
Interrupt
16-16.
Yes
Yes
16-25