MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 419

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
(see notes)
Configured
MTMOD
MTMOD
MTMOD
MTMOD
by
4
4
4
4
1
PWM_OUT0
QSPI_Dout/
QSPI_CLK/
QSPI_CS0/
QSPI_Din
0 (Reset)
SDCLKE
BYPASS
BUSW1
BUSW0
SDBA0
SDBA1
SDCLK
SDCS/
SDWE
WSEL
RSTO
PST3
RAS0
TEST
RSTI
TDO
TIN0
TMS
TCK
R/W
CS7
TEA
TDI
Table 19-1. Signal Descriptions Sorted by Function (Sheet 7 of 8)
MCF5272 ColdFire
Pin Functions
PSTCLK
BKPT
DSO
DSI
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1
®
Integrated Microprocessor User’s Manual, Rev. 3
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3
Internal processor status
3
PWM output compare 0
QSPI serial clock/CS0
bus width bit 1
QSPI peripheral chip
select 0/CS0 bus width
bit 0
QSPI data input
QSPI data output/Bus
width selection
Read/Write
SDRAM row select
strobe
Device reset
Reset output strobe
SDRAM bank 0 select
SDRAM bank 1 select
SDRAM (bus) clock,
Same frequency as CPU
clock
SDRAM clock enable
SDRAM chip select/CS7
SDRAM write enable
Bypass internal test
mode
JTAG test clock in/
BDM PSTCLK output
JTAG test data in/BDM
data in
JTAG test data out
/BDM data out
BDM debug transfer error
acknowledge
Device test mode enable
Timer 0 input
JTAG test mode/BDM
select breakpoint input
Description
BGA
Map
M12
M13
P14
A10
H12
E14
D13
B10
Pin
J14
M5
D3
N5
P4
N4
B9
C4
A4
D5
A3
E6
B4
L5
F4
L6
Signal Descriptions
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Drive
(mA)
10
10
10
10
10
10
10
10
4
4
4
2
4
4
4
4
4
Cpf
19-9
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30