MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 27

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Paragraph
Number
19.13 Ethernet Module Signals ........................................................................................................ 19-27
19.14 PWM Module Signals (PWM_OUT0–PWM_OUT2]) ......................................................... 19-29
19.15 Queued Serial Peripheral Interface (QSPI) Signals ............................................................... 19-29
19.16 Physical Layer Interface Controller TDM Ports and UART 1 .............................................. 19-31
Freescale Semiconductor
19.13.1 Transmit Clock (E_TxCLK) ....................................................................................... 19-27
19.13.2 Transmit Data (E_TxD0) ............................................................................................ 19-28
19.13.3 Collision (E_COL) ..................................................................................................... 19-28
19.13.4 Receive Data Valid (E_RxDV) ................................................................................... 19-28
19.13.5 Receive Clock (E_RxCLK) ........................................................................................ 19-28
19.13.6 Receive Data (E_RxD0) ............................................................................................. 19-28
19.13.7 Transmit Enable (E_TxEN) ........................................................................................ 19-28
19.13.8 Transmit Data (E_TxD[3:1]/PB[10:8]) ...................................................................... 19-28
19.13.9 Receive Data (E_RxD[3:1]/PB[13:11]) ...................................................................... 19-28
19.13.10 Receive Error (E_RxER/PB14) ................................................................................ 19-29
19.13.11 Management Data Clock (E_MDC/PB15) ............................................................... 19-29
19.13.12 Management Data (E_MDIO) .................................................................................. 19-29
19.13.13 Transmit Error (E_TxER) ......................................................................................... 19-29
19.13.14 Carrier Receive Sense (E_CRS) ............................................................................... 19-29
19.15.1 QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL) .................................... 19-30
19.15.2 QSPI Synchronous Serial Data Input (QSPI_Din) ..................................................... 19-30
19.15.3 QSPI Serial Clock (QSPI_CLK/BUSW1) .................................................................. 19-30
19.15.4 Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0) ................................... 19-30
19.15.5 Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11) ........................................ 19-30
19.15.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) .............................. 19-30
19.15.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3) ............................ 19-30
19.16.1 GCI/IDL TDM Port 0. ................................................................................................ 19-31
19.16.2 GCI/IDL TDM Port 1 ................................................................................................. 19-32
19.16.1.1 Frame Sync (FSR0/FSC0/PA8) .................................................................... 19-31
19.16.1.2 D-Channel Grant (DGNT0/PA9) .................................................................. 19-31
19.16.1.3 Data Clock (DCL0/URT1_CLK) .................................................................. 19-31
19.16.1.4 Serial Data Input (DIN0/URT1_RxD) .......................................................... 19-31
19.16.1.5 UART1 CTS (URT1_CTS/QSPI_CS2) ........................................................ 19-32
19.16.1.6 UART1 RTS (URT1_RTS/INT5) ................................................................. 19-32
19.16.1.7 Serial Data Output (DOUT0/URT1_TxD) ................................................... 19-32
19.16.1.8 D-Channel Request(DREQ0/PA10) ............................................................. 19-32
19.16.1.9 QSPI Chip Select 1 (QSPI_CS1/PA11) ........................................................ 19-32
19.16.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT) ............................................... 19-32
19.16.2.2 GCI/IDL Data Out (DOUT1) ....................................................................... 19-33
19.16.2.3 GCI/IDL Data In (DIN1) .............................................................................. 19-33
19.16.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ............................................... 19-33
19.16.2.5 D-Channel Request (DREQ1/PA14) ............................................................ 19-33
MCF5272 ColdFire
Table of Contents (Continued)
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Integrated Microprocessor User’s Manual, Rev. 3
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