MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 117

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Bits
4–3
1–0
6
5
2
Name
BWE
CM
WP
—
—
Cache mode. Defines whether the memory access is cacheable or noncacheable.
0 Caching enabled
1 Caching disabled
Buffered write enable. Generally, the enabling of buffered writes provides higher system performance but
recovery from access errors may be more difficult. For the ColdFire CPU, reporting access errors on operand
writes is always imprecise; enabling buffered writes further decouples the write instruction from the signaling
of the fault.
0 Termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle
1 A write cycle on the local bus is terminated immediately and the operation is then buffered in the bus
Reserved, should be cleared.
Write protect. Selects the write privilege of the memory region.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
is completed.
controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus
and the external bus.
MCF5272 ColdFire
Table 4-9. ACRn Field Descriptions (continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Local Memory
4-15