MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 133

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.5
The ColdFire Family implements a low-level system debugger in the microprocessor hardware.
Communication with the development system is handled through a dedicated, high-speed serial command
interface. The ColdFire architecture implements the BDM controller in a dedicated hardware module.
Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM
commands, such as memory accesses, can be executed while the processor is running.
Freescale Semiconductor
20–18/4
28–22
28/12
27/11
26/10
12–6
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
Bits
–2
Name
Background Debug Mode (BDM)
EPC
EDx
EAx
PCI
DI
Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement
on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
EDLW
EDWL
EDWU
EDLL
EDLM
EDUM
EDUU
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators.
This can develop a trigger based on the occurrence of a data value other than the DBR contents.
Enable address bits. Setting an EA bit enables the corresponding address breakpoint. Clearing all three bits
disables the breakpoint.
EAI
EAR
EAL
Enable PC breakpoint. If set, this bit enables the PC breakpoint.
Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR and PBMR to
enable a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and PBMR.
MCF5272 ColdFire
Data longword. Entire processor’s local data bus.
Lower data word.
Upper data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Upper upper data byte. High-order byte of the high-order word.
Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR and
ABHR.
Enable address breakpoint range. The breakpoint is based on the inclusive range defined by
ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the address in the ABLR.
Table 5-14. TDR Field Descriptions (continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Debug Support
5-15